A memory array, such as a flash memory array, includes bitlines, wordlines, which run in a direction perpendicular to the bitlines, and memory cells, which are situated at the intersection of each wordline and bitline. To program a memory cell, which is situated at the intersection of a wordline and a bitline, wordline and bitline programming voltages must be applied to the respective wordline and bitline. In a memory array, such as a flash memory array, a bitline select transistor must typically be turned on for the bitline programming voltage to be applied to a selected bitline. In the memory array, a bitline select driver circuit typically provides the high output voltage required to turn on the bitline select transistor.
However, to provide the high output voltage required to turn on the bitline select transistor, the conventional bitline select driver utilizes a correspondingly high supply voltage. As a result of the high supply voltage, the conventional bitline select driver circuit requires a snap back protection transistor, which undesirably increases layout size. Also, the high supply voltage undesirably reduces the switching speed of the conventional bitline select driver circuit.
Thus, there is a need in the art for reduced layout size and increased switching speed in a bitline select driver circuit in a memory array, such as a flash memory array.